SystemLisp - an HDL simulator written in Common Lisphttps://github.com/systemlisp#lisp #commonlisp #hdl #rtl #verilog #design #verification #vhdl #systemverilog #vlsi #programming #fpga
Has anyone tried Chisel? How is it compared to Verilog/SystemVerilog in terms of efficiency, productivity, and performance?#hdl #rtl #chisel #verilog #systemverilog
