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[TSKaigi 2026]の登壇者募集、数日前に締め切られたんだな。私が出したプロポーザルは通るかな?

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  • we're seeing nightmare levels at about 87%

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    @levelbot we sure are
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    Italians vote in high-stakes justice referendum in key test for Melonihttps://www.aljazeera.com/news/2026/3/22/italians-vote-in-high-stakes-justice-referendum-in-key-test-for-meloni?traffic_source=rss> Right-wing PM Giorgia Meloni faces a political test in the two-day referendum on contested judicial reform.
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    Do you have a friend who is a decent person with great skills? Introduce them to friends or acquaintances who one day might hire your friend. Just let them know each other.Build a support network for your friend now, before they need a job. Don't wait for your friend to get fired and scramble for openings, have opportunities and connections ready.
  • Building a $50 SDR with 20 MHz Bandwidth

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    Building a $50 SDR with 20 MHz BandwidthAlthough the RTL-SDR is cheap, accessible, and capable enough for many projects, it does have some important limitations. In particular, its bandwidth is limited to about 3.2 MHz, and the price of SDRs tends to scale rapidly with bandwidth. [Anders Nielsen], however, is building a modular SDR with a target price of $50 USD, and has already reached a bandwidth of almost 20 MHz.If this project looks familiar, it’s because we’ve covered an earlier iteration. At the time, [Anders] had built the PhaseLoom, which filters an incoming signal, mixes it down to baseband, and converts it to I/Q signals. The next stage is the PhaseLatch, a board housing a 20-MHz, 10-bit ADC, which samples the in-phase and quadrature signals and passes them on to a Cypress FX2LP microcontroller development board. [Anders] had previously connected the ADC to a 6502 microprocessor instead of the FX2LP, but this makes it a practical SDR. The FX2LP was a particularly good choice for this project because of its USB 2.0 interface, large buffers for streaming data, and parallel interface. It simply reads the data from the SDR and dumps it to the computer.The FX2LP didn’t support the ADC’s clock rate, and overclocking the ADC led to issues, so [Anders] connected the ADC to an independent 20 MHz oscillator. The frequency spectrum of the SDR was oddly bell-shaped, which turned out to be due to the limited analogue bandwidth of the PhaseLoom (about 650 kHz) falling behind the digital bandwidth of 20 MHz. The PhaseLoom’s bandwidth seemed to be limited mostly by an amplifier, and decreasing its gain greatly improved matters. The SDR doesn’t yet have a 20 MHz bandwidth according to the normal definition, but it’s close enough to be practical, and further improvements will have to wait on an updated PhaseLoom board.The Cypress development board used here is surprisingly capable – we’ve previously seen it used to build an SDR GPS decoder. Most of the custom-built SDRs we see don’t focus on technical performance, but do use such interesting components as a tube-based receiver or a custom silicon chip.youtube.com/embed/gf1M8sVMaNA?…hackaday.com/2026/03/22/buildi…