@spacehobo That would be interesting indeed.

[amoroso@oldbytes.space]

@spacehobo That would be interesting indeed.

[dougmerritt@mathstodon.xyz]

@amoroso @spacehobo
As someone who has worked on compilers *and* FPGAs on and off for decades (and I've written Verilog):

The author doesn't know what they're talking about. There *is* a problem with crufty toolchains, but the problem is *not* the design of Verilog nor VHDL, that's outright stupid.

It's as if someone said the industry was being held back by programming in Pascal. It's not my favorite language but it gets the job done. It's not the central problem.

And if they do have some *specific* complaint about Verilog or VHDL, then they should say what it is, not just indulge in vague finger pointing -- which is never productive.

[amoroso@oldbytes.space]

@dougmerritt Some kind of proposal of how to improve traditional languages is conspicuously missing.

@spacehobo